1. Field of the Invention
The present invention relates to compression of numerical data represented in a floating-point format or an integer format for efficient storage and transfer in a computing system. In particular, the floating-point data are converted to integer, or fixed-point, representations prior to compression processing.
2. Description of Related Art
In present high performance computing applications, it is often necessary to transfer vast amounts of numerical data among multiple processor cores or between processor cores and memory. The limited data transfer rates of interfaces among processor cores and between cores and memory devices can create bottlenecks for overall data processing speed and performance. In data rich applications, storage of numerical data challenges memory and network resources and storage devices. Reducing the demands on data transfer and storage capacity for numerical data can improve the efficiency, economy and performance of the computing system. Compression of the numerical data may reduce these demands, however at the cost of additional computations. In applications having vast quantities of numerical data, it is especially important that the compression be computationally efficient in order to minimize demands on computing resources.
Commonly owned patents and applications describe a variety of compression techniques applicable to fixed-point, or integer, representations of numerical data or signal samples. These include U.S. Pat. No. 5,839,100 (the '100 patent), entitled “Lossless and loss-limited Compression of Sampled Data Signals” by Wegener, issued Nov. 17, 1998, and the U.S. patent application Ser. No. 12/605,245 (the '245 application), entitled “Block Floating Point Compression of Signal Data,” publication number 2011-0099295, published Apr. 28, 2011. The commonly owned patent application Ser. No. 12/891,312 (the '312 application), entitled “Enhanced Multi-processor Waveform Data Exchange Using Compression and Decompression,” by Wegener, publication number 2011-0078222, published Mar. 31, 2011, incorporated herein by reference, describes configurable compression and decompression for fixed-point or floating-point data types in computing systems having multi-core processors. In a multi-core processing environment, input, intermediate, and output waveform data are often exchanged among cores and between cores and memory devices. The '312 application describes a configurable compressor/decompressor at each core that can compress/decompress integer or floating-point waveform data. The '312 application describes configurable compression/decompression at the memory controller to compress/decompress integer or floating-point waveform data for transfer to/from off-chip memory in compressed packets. The configurable compressor and decompressor of the '312 application may be configured to apply the compression and decompression described in the present application. The commonly owned non-provisional patent application Ser. No. 13/534,330, filed Jun. 27, 2012, entitled “Computationally Efficient Compression of Floating-Point Data,” describes algorithms for direct compression floating-point data by processing the exponent values and the mantissa values of the floating-point format.
FIG. 1 is a diagram illustrating an example of a floating-point data format used in a computing system. This floating-point format is presented for illustrative purposes only. The compression and decompression described herein are not limited to this particular representation of floating-point data. In FIG. 1, the floating-point format represents a floating-point number 10 by an array of binary bits. The floating-point number 10 occupies a number of bits NB that include a single sign bit 12, the number of bits NE representing an exponent 14 and the number of bits NM representing a mantissa 16, also referred to as a significand. The sign bit 12 has a value of s=0 for positive numbers and s=1 for negative numbers. The numbers of bits NB, NE and NM may be specified by the floating-point format. For example, the IEEE-754 Standard for Floating-Point Arithmetic, referred to as “IEEE-754 standard”, defines single precision and double precision floating-point formats. For single precision, the number of bits NB=32, the number of exponent bits NE=8 and the number of mantissa bits NM=23. To construct a single precision floating-point number from a fixed-point binary number, the leading “1” of the binary fixed-point number is shifted to the left of the binary point and the fractional part is stored in NM bits of the floating-point mantissa 16. The leading “1” is not stored in the floating-point mantissa 16. In order to store only positive values for the floating-point exponent 14, an exponent bias of 127 is added to the value of the exponent. The value of the single precision floating-point number in sign and magnitude notation is given by,(−1)s×1.m×2(e−e0)  (1)where s is the value of the sign bit 12, m is the binary value of the mantissa 16, e is the binary value of the exponent 14 and e0=127, the exponent bias for single precision. For e0=127, the exponent term (e−e0) in equation (1) can be any value in the range of −127≦(e−e0)≦128. For double precision floating-point format, the IEEE-754 standard specifies the number of bits NB=64, the number of exponent bits NE=11, the number of mantissa bits NM=52 and the exponent bias e0=1023. In equation (1), the “1.m” term contains a “1” before the binary point that is not explicitly encoded in the mantissa “m”, but is implicit in the floating-point format. The implicit “1” is referred to as the “hidden bit”.
In order to better meet the requirements of higher speed data transfer, reduced memory utilization and minimal computation in many computing applications, a need exists for computationally efficient compression and decompression of floating-point data and integer data.